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ai01020 13 a0-a12 w dq0-dq7 v cc m48t08 m48t18 g e2 v ss 8 e1 int figure 1. logic diagram m48t08 m48t18 cmos 8k x 8 timekeeper sram integrated ultra low power sram, real time clock and power-fail control circuit bytewide ram-like clock access bcd coded year, month, day, date, hours, minutes and seconds clock accuracy of 1 minute a month, @ 25 c software controlled clock calibration for high accuracy applications automatic power-fail chip deselect and write protection choice of two write protect voltages: m48t08: 4.5v v pfd 4.75v m48t18: 4.2v v pfd 4.5v self contained battery and crystal in the caphat dip package small outline package provides direct connection for a snaphat housing containing the battery and crystal snaphat housing (battery and crystal) replaceable 10 years of data retention and clock operation in the absence of power pin and function compatible with jedec standard 8k x 8 srams a0-a12 address inputs dq0-dq7 data inputs / outputs int power fail interrupt e1 chip enable 1 e2 chip enable 2 g output enable w write enable v cc supply voltage v ss ground table 1. signal names 28 1 pcdip28 (pc) battery caphat 28 1 soh28 (mh) battery snaphat november 1994 1/18
symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) 40 to 85 c v io input or output voltages 0.3 to 7 v v cc supply voltage 0.3 to 7 v i o output current 20 ma p d power dissipation 1 w note: stresses greater than those listed under oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. caution: negative undershoots below 0.3 volts are not allowed on any pin while in the battery back-up mode. table 2. absolute maximum ratings mode v cc e1 e2 g w dq0-dq7 power deselect 4.75v to 5.5v or 4.5v to 5.5v v ih x x x high z standby deselect x v il x x high z standby write v il v ih xv il d in active read v il v ih v il v ih d out active read v il v ih v ih v ih high z active deselect v so to v pfd (min) xxxx high z cmos standby deselect v so xxxx high z battery back-up mode note :x=v ih or v il table 3. operating modes a1 a0 dq0 a7 a4 a3 a2 a6 a5 e2 a10 a8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 int v cc ai01182 m48t08 m48t18 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 figure 2a. dip pin connections ai01021b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 e2 a10 a8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 int v cc m48t08 m48t18 figure 2b. so pin connections 2/18 m48t08, m48t18
ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k w device under test 1k w figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. ai01333 lithium cell oscillator and clock chain v pfd int v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 biport sram array 8184 x 8 sram array a0-a12 dq0-dq7 e1 e2 w g power figure 3. block diagram description the m48t08,18 timekeeper ? ram is an 8k x 8 non-volatile static ram and real time clock which is pin and functional compatible with the mk48t08,18. the monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. the m48t08,18 is a non-volatile pin and function equivalent to any jedec standard 8k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28 pin 600mil dip caphat ? houses the m48t08,18 silicon with a quartz crystal and a long life lithium button cell in a single package. the 28 pin 330mil so provides sockets with gold plated contacts at both ends for direct connection to a separate snaphat ? housing containing the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the so package after the completion of the surface mount process. 3/18 m48t08, m48t18
symbol parameter test condition min max unit i li (1) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 5 m a i cc supply current outputs open 80 ma i cc1 (2) supply current (standby) ttl e1 = v ih ,e2=v il 3ma i cc2 (2) supply current (standby) cmos e1 = v cc 0.2v, e2 = v ss + 0.2v 3ma v il (3) input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v output low voltage (int) (4) i ol = 0.5ma 0.4 v v oh output high voltage i oh = 1ma 2.4 v notes: 1. outputs deselected. 2. measured with control bits set as follows: r = '1'; w, st, ft = '0'. 3. negative spikes of 1v allowed for up to 10ns once per cycle. 4. the int pin is open drain. table 5. dc characteristics (t a =0 to70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) symbol parameter test condition min max unit c in input capacitance v in =0v 10 pf c io (2) input / output capacitance v out =0v 10 pf notes: 1. effective capacitance calculated from the equation c = i d t/ d v with d v = 3v and power supply at 5v. 2. outputs deselected table 4. capacitance (1) (t a =25 c, f = 1 mhz ) symbol parameter min typ max unit v pfd power-fail deselect voltage (m48t08) 4.5 4.6 4.75 v v pfd power-fail deselect voltage (m48t18) 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr (2) expected data retention time 10 years notes: 1. all voltages referenced to v ss . 2. @ 25 c table 6. power down/up trip points dc characteristics (1) (t a =0to70 c) insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting.the snaphat housing is keyed to prevent reverse insertion. the so and battery packages are shipped sepa- rately in plastic anti-static tubes. the so package is also available to ship in tape & reel form. for the28leadso,thebatterypackage(i.e. snaphat) part number is om4t28-br12sh1o. as figure 3 shows, the static memory array and the quartz controlled clock oscillator of the m48t08,18 are integrated on one silicon chip. the two circuits are interconnected at the upper eight memory lo- cations to provide user accessible bytewide ? clock information in the bytes with addresses 1ff8h-1fffh. the clock locations contain the year, month, date, day, hour, minute, and second in description (cont'd) 4/18 m48t08, m48t18
symbol parameter min max unit t pd e1 or w at v ih or e2 at v il before power down 0 m s t f (1) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (2) v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 0 m s t rb v so to v pfd (min) v cc rise time 1 m s t rec e1 or w at v ih or e2 at v il after power up 1 ms t pfx int low to auto deselect 10 40 m s t pfh (3) v pfd (max) to int high 120 m s notes :1.v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 m s after v cc passes v pfd (min). 2. v pfd (min) to v so fall time of less than t fb may cause corruption of ram data. 3. int may go high anytime after v cc exceeds v pfd (min) and is guaranteed to go high t pfh after v cc exceeds v pfd (max). table 7. power down/up mode ac characteristics (t a = 0 to 70 c) ai00566 v cc inputs int (per control input) outputs don't care high-z tf tfb tpfx tr tpfh trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so figure 5. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e1high or e2 low as v cc rises past v pfd (min). some systems may performs inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begins. even though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running. 5/18 m48t08, m48t18
symbol parameter m48t08 / 18 unit -100 -150 min max min max t avav read cycle time 100 150 ns t avqv address valid to output valid 100 150 ns t e1lqv chip enable 1 low to output valid 100 150 ns t e2hqv chip enable 2 high to output valid 100 150 ns t glqv output enable low to output valid 50 75 ns t e1lqx chip enable 1 low to output transition 10 10 ns t e2hqx chip enable 2 high to output transition 10 10 ns t glqx output enable low to output transition 5 5 ns t e1hqz chip enable 1 high to output hi-z 50 75 ns t e2lqz chip enable 2 low to output hi-z 50 75 ns t ghqz output enable high to output hi-z 40 60 ns t axqx address transition to output transition 5 5 ns table 8. read mode ac characteristics (t a =0to70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) ai00962 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz valid a0-a12 e1 g dq0-dq7 te2hqv te2hqx valid te2lqz e2 figure 6. read mode ac waveforms 6/18 m48t08, m48t18
symbol parameter m48t08 / 18 unit -100 -150 min max min max t avav write cycle time 100 150 ns t avwl address valid to write enable low 0 0 ns t ave1l address valid to chip enable 1 low 0 0 ns t ave2h address valid to chip enable 2 high 0 0 ns t wlwh write enable pulse width 80 100 ns t e1le1h chip enable 1 low to chip enable 1 high 80 130 ns t e2he2l chip enable 2 high to chip enable 2 low 80 130 ns t whax write enable high to address transition 10 10 ns t e1hax chip enable 1 high to address transition 10 10 ns t e2lax chip enable 2 low to address transition 10 10 ns t dvwh input valid to write enable high 50 70 ns t dve1h input valid to chip enable 1 high 50 70 ns t dve2l input valid to chip enable 2 low 50 70 ns t whdx write enable high to input transition 5 5 ns t e1hdx chip enable 1 high to input transition 5 5 ns t e2ldx chip enable 2 low to input transition 5 5 ns t wlqz write enable low to output hi-z 50 70 ns t avwh address valid to write enable high 80 130 ns t ave1h address valid to chip enable 1 high 80 130 ns t ave2l address valid to chip enable 2 low 80 130 ns t whqx write enable high to output transition 10 10 ns table 9. write mode ac characteristics (t a = 0 to 70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) 7/18 m48t08, m48t18
ai00963 tavav twhax tdvwh data input a0-a12 e1 w dq0-dq7 valid e2 tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx figure 7. write enable controlled, write ac waveforms ai00964b tavav te1hax tdve1h tdve2l a0-a12 e1 w dq0-dq7 valid e2 tave1h tave1l tavwl tave2l te1le1h te2lax tave2h te2he2l te1hdx te2ldx data input figure 8. chip enable controlled, write ac waveforms 8/18 m48t08, m48t18
24 hour bcd format. corrections for 28, 29 (leap year), 30, and 31 day months are made automat- ically. byte 1ff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport ? read/write memory cells. the m48t08,18 includes a clock control circuit which updates the clock bytes with current informa- tion once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t08,18 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system opera- tion brought on by low v cc .asv cc falls below approximately 3v, the control circuitry connects the battery which maintains data and clock operation until valid power returns. read mode the m48t08,18 is in the read mode whenever w (write enable) is high, e1 (chip enable 1) is low, and e2 (chip enable 2) is high. the device archi- tecture allows ripple- through access of data from eight of 65,536 locations in the static storage array. thus, the unique address specified by the 13 ad- dress inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be avail- able at the data i/o pins within t avqv (address access time) after the last address input signal is stable, providing that the e1, e2, and g access times are also satisfied. if the e1, e2 and g access times are not met, valid data will be available after the latter of the chip enable access times (t e1lqv or t e2hqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e1, e2 and g. if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e1, e2 and g remain active, output data will remain valid for t axqx (out- put data hold time) but will go indeterminate until the next address access. write mode the m48t08,18 is in the write mode whenever w, e1, and e2 are active. the start of a write is refer- enced from the latter occurring falling edge of w or e1, or the rising edge of e2. a write is terminated by the earlier rising edge of w or e1, or the falling edge of e2. the addresses must be held valid throughout the cycle. e1 or w must return high or e2 low for minimum of t e1hax or t e2lax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e1 and g and a high on e2, a low on w will disable the outputs t wlqz after w falls. data retention mode with valid v cc applied,the m48t08,18 operates as a conventional bytewide static ram. should the supply voltage decay, the ram will automatically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as odon't care.o note: a power failure during a write cycle may corrupt data at the currentlyaddressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be as- sured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t08,18 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recom- mended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data and powers the clock. the internal button cell will maintain data in the m48t08,18 for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min). e1 should be kept high or e2 low as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to processor stabilization. normal ram operationcan resume t rec after v cc exceeds v pfd (max). power fail interrupt pin the m48t08,18 continuously monitors v cc .when v cc falls to the power-fail detect trip point, an interrupt is immediately generated. an internal clock provides a delay of between 10 m s and 40 m s before automatically deselecting the m48t08,18. the int pin is an open drain output and requires an external pull up resistor, even if the interrupt output function is not being used. description (cont'd) 9/18 m48t08, m48t18
system battery life the useful life of the battery in the m48t08,18 is expected to ultimately come to an end for one of two reasons: either because it has been discharged while providing current to the ram and clock in the battery back-up mode, or because the effects of aging render the cell useless before it can actually be completely discharged. the two effects are vir- tually unrelated allowing discharge, or capacity consumption, and the effects of aging, or storage life, to be treated as two independent but simulta- neous mechanisms. the earlier occurring failure mechanism defines the battery system life of the m48t08,18. cell storage life storage life is primarily a function of temperature. figure 9 illustrates the approximate storage life of the m48t08,18 battery over temperature. the re- sults in figure 9 are derived from temperature accelerated life test studies performed at sgs- thomson. for the purpose of the testing, a cell failure is defined as the inability of a cell stabilized at 25 c to produce a 2.4v closed circuit voltage across a 250 k w load resistor. the two lines, t 1% and t 50% , represent different failure rate distribu- tions for the cell's storage life. at 70 c, for example, the t 1% line indicates that an m48t08,18 has a 1% chance of having a battery failure 11 years into its life while the t 50% shows the part has a 50% chance of failure at the 20 year mark. the t 1% line repre- sents the practical onset of wear out and can be considered the worst case storage life for the cell. the t 50% can be considered the normal or average life. calculating storage life the following formula can be used to predict stor- age life: 1 {[(ta1/tt)/sl1]+[(ta2/tt)/sl2]+...+[(tan/tt)/sln]} where, ta1, ta2, tan = time at ambient temperature 1, 2, etc. tt = total time = ta1+ta2+...+tan sl1, sl2, sln = storage life at temperature 1, 2, etc. for example an m48t08,18 is exposed to tempera- tures of 55 c or less for 8322 hrs/yr, and tempera- tures greater than 60 c but less than 70 c for the remaining 438 hrs/yr. reading predicted t 1% values from figure 9, ai01024 20 30 40 50 60 70 80 90 1 2 3 4 5 8 6 temperature (degrees celsius) 10 20 30 40 50 years t50% (average) t1% figure 9. predicted battery storage life versus temperature 10/18 m48t08, m48t18
sl1 = 41 yrs, sl2 = 11.4 yrs tt = 8760 hrs/yr ta1 = 8322 hrs/yr, ta2 = 438 hrs/yr predicted storage life 1 {[(8322/8760)/41]+[(431/8760)/11.4]} or 36 years. cell capacity life the m48t08,18 internal cell has a rated capacity of 50mah. the device places a nominal ram and timekeeper load of less than 520na at room temperature. at this rate, the capacity consumption life is 50e-3/520e-9 = 96,153 hours or about 11 years. capacity consumption life can be extended by applying v cc or turning off the clock oscillator prior to system power down. calculating capacity life the ram and timekeeper load remains rela- tively constant over the operating temperature range. thus, worst case cell capacity life is essen- tially a function of one variable, v cc duty cycle. for example, if the oscillator runs 100% of the time with v cc applied 60% of the time, the capacity con- sumption life is 10/(1-0.6), or 25 years. estimated system life since either storage life or capacity consumption can end the battery's life, the system life is marked by which ever occurs first. in the above example, this would be 25 years. reference for system life each m48t08,18 is marked with a nine digit manu- facturing date code in the form of h99xxyyzz. for example, h995b9431 is: h = fabricated in carrollton, tx 9 = assembled in muar, malaysia, 9 = tested in muar, malaysia, 5b = lot designator, 9431 = assembled in the year 1994, work week 31. clock operations reading the clock updates to the timekeeper registers should be halted before clock data is read to prevent reading data in transition. because the biport time- keeper cells in the ram array are only data registers, and not the actual clock counters, updat- ing the registers can be halted without disturbing the clock itself. updating is halted when a '1' is written to the read bit, the seventh bit in the control register. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0'. setting the clock the eighth bit of the control register is the write bit. setting the write bit to a '1', like the read bit, halts updates to the timekeeper registers. the user can then load them with the correct day, date, and time data in 24 hour bcd format (see table 10). resetting the write bit to a '0' then transfers the values of all time registers (1ff9h-1fffh) to the actual timekeeper counters and allows nor- mal operation to resume. the ft bit and the bits marked as '0' in table 10 must be written to '0' to allow for normal timekeeper and ram opera- tion. stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. settingit to a '1' stops the oscillator. the m48t08,18 is shippedfrom sgs-thomson with the stop bit set to a '1'. when reset to a '0', the m48t08,18 oscillator starts within 1 second. calibrating the clock the m48t08,18 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. a typical m48t08,18 is accurate within 1 minute per month at 25 c without calibration. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 c, which equates to about 1.53 minutes per month. of course the oscillation rate of any crystal changes with tem- perature. figure 11 shows the frequency error that can be expected at various temperatures. most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim ca- pacitors. the m48t08,18 design, however, em- ploys periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in figure 10. the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits in the control register. this byte can be set to represent any value between 0 and 31 in binary 11/18 m48t08, m48t18
form. the sixth bit is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. cali- bration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or - 5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t08,18 may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final prod- uct is packaged in a non-user serviceable enclo- sure. all the designer has to do is provide a simple utility that accesses the calibration byte. the utility could even be menu driven and made foolproof. the second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the day register, is set to a '1', and the oscillator is running at 32,768 hz, the lsb (dq0) of the seconds reg- ister will toggle at 512 hz. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for exam- ple, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a -10(001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. the device must be selected and addresses must stable at address 1ff9h when reading the 512 hz on dq0. the ft bit must be set using the same method used to set the clock, using the write bit. the lsb of the seconds register is monitored by holding the m48t08,18 in an extended read of the seconds register, without having the read bit set. the ft bit must be reset to '0' for normal clock operations to resume. address data function/ran ge bcd format d7 d6 d5 d4 d3 d2 d1 d0 1fffh 10 years year year 00-99 1ffeh 0 0 0 10 m. month month 01-12 1ffdh 0 0 10 date date date 01-31 1ffch 0 ft 0 0 0 day day 01-07 1ffbh 0 0 10 hours hours hour 00-23 1ffah 0 10 minutes minutes minutes 00-59 1ff9h st 10 seconds seconds seconds 00-59 1ff8h w r s calibration control keys: s = sign bit ft = frequency test bit (set to '0' for normal clock operation) r = read bit w = write bit st = stop bit 0 = must be set to '0' table 10. register map clock operations (cont'd) 12/18 m48t08, m48t18
ai00594 normal positive calibration negative calibration figure 10. clock calibration ai01025 0 10203040 60 50 80 70 60 50 40 30 10 20 20 temperature (degees celsius) 70 10 0 frequency error (ppm) figure 11. crystal frequency error 13/18 m48t08, m48t18
ordering information scheme supply voltage and write protect voltage 08* v cc = 4.75v to 5.5v v pfd = 4.5v to 4.75v 18 v cc = 4.5v to 5.5v v pfd = 4.2v to 4.5v speed -100 100ns -150 150ns package pc pcdip28 mh soh28 temp. range 1 0to70 c shipping method for so blank tubes tr tape &reel example: m48t18 -100 mh 1 tr the so and battery packages are shipped separately in plastic anti-static tubes. the so package is also available to ship in tape & reel form. for the m48t18 28 lead so, the battery package (i.e. snaphat) part number is om4t28-br12sh1o. for a list of available options (supply voltage, speed, package, etc...) refer to the current memory shortform catalogue. for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. note: 08* caphat package only. 14/18 m48t08, m48t18
pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28 pcdip28 drawing is not to scale pcdip28 - 28 pin plastic dip, battery caphat 15/18 m48t08, m48t18
soh e n d c l a1 a 1 h a cp be a2 eb symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 0.050 eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 soh28 drawing is not to scale soh28 - 28 lead plastic small outline, battery snaphat 16/18 m48t08, m48t18
sh a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 sh28 sh28 - snaphat housing for 28 lead plastic small outline drawing is not to scale 17/18 m48t08, m48t18
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved ? timekeeper, snaphat, caphat, bytewide and biport are trademarks of sgs-thomson microelectronics sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 18/18 m48t08, m48t18
ai01022 13 a0-a12 w dq0-dq7 v cc m48z08 m48z18 g v ss 8 e figure 1. logic diagram m48z08 m48z18 cmos 8k x 8 zeropower sram integrated ultra low power sram, power-fail control circuit and battery unlimited write cycles read cycle time equals write cycle time automatic power-fail chip deselect and write protection choice of two write protect voltages: m48z08: 4.5v v pfd 4.75v m48z18: 4.2v v pfd 4.5v self contained battery in the caphat dip package small outline package provides direct connection for a snaphat housing containing the battery snaphat housing (battery) replaceable 11 years of data retention in the absence of power pin and function compatible with the mk48z08, 18 and jedec standard 8k x 8 srams description the m48z08,18 zeopower ? ram is an 8k x 8 non-volatile static ram which is pin and functional compatible with the mk48z08,18. the monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory so- lution. a0-a12 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground table 1. signal names 28 1 pcdip28 (pc) battery caphat 28 1 soh28 (mh) battery snaphat november 1994 1/15
symbol parameter value unit t a ambient operating temperature grade 1 grade 6 0to70 40 to 85 c t stg storage temperature (v cc off) 40 to 85 c v io input or output voltages 0.3 to 7 v v cc supply voltage 0.3 to 7 v i o output current 20 ma p d power dissipation 1 w note: stresses greater than those listed under oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. caution: negative undershoots below 0.3 volts are not allowed on any pin while in the battery back-up mode. table 2. absolute maximum ratings mode v cc e g w dq0-dq7 power deselect 4.75v to 5.5v or 4.5v to 5.5v v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) x x x high z cmos standby deselect v so x x x high z battery back-up mode note :x=v ih or v il table 3. operating modes a1 a0 dq0 a7 a4 a3 a2 a6 a5 nc a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 nc v cc ai01183 m48z08 m48z18 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 figure 2a. dip pin connections ai01023b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 nc a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 nc v cc m48z08 m48z18 figure 2b. so pin connections warning: nc = not connected warning: nc = not connected 2/15 m48z08, m48z18
ai01398 5v out c l = 100pf or 30pf c l includes jig capacitance 1.8k w device under test 1k w figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. ai01394 lithium cell v pfd v cc v ss voltage sense and switching circuitry 8k x 8 sram array a0-a12 dq0-dq7 e w g power figure 3. block diagram the m48z08,18 is a non-volatile pin and function equivalent to any jedec standard 8k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28 pin 600mil dip caphat ? houses the m48z08,18 silicon with a long life lithium button cell in a single package. the 28 pin 330mil so provides sockets with gold plated contacts at both ends for direct connection to a separate snaphat ? housing containing the battery. the unique design allows the snaphat battery package to be mounted on top of the so package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the so and battery packages are shipped sepa- rately in plastic anti-static tubes. the so package is also available to ship in tape & reel form. description (cont'd) 3/15 m48z08, m48z18
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 5 m a i cc supply current outputs open 80 ma i cc1 supply current (standby) ttl e = v ih 3ma i cc2 supply current (standby) cmos e = v cc 0.2v 3 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = 1ma 2.4 v table 5. dc characteristics (t a =0 to70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) symbol parameter test condition min max unit c in input capacitance v in =0v 10 pf c io (2) input / output capacitance v out =0v 10 pf notes: 1. effective capacitance calculated from the equation c = i d t/ d v with d v = 3v and power supply at 5v. 2. outputs deselected table 4. capacitance (1) (t a =25 c) symbol parameter min typ max unit v pfd power-fail deselect voltage (m48z08) 4.5 4.6 4.75 v v pfd power-fail deselect voltage (m48z18) 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr expected data retention time 11 years note: 1. all voltages referenced to v ss . table 6. power down/up trip points dc characteristics (1) (t a =0to70 c) for the 28 lead so, the battery package (i.e. snaphat) part number is om4z28-br00sh1o. the m48z08,18 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictablesystem opera- tion brought on by low v cc .asv cc falls below approximately 3v, the control circuitry connects the battery which maintains data until valid power re- turns. description (cont'd) 4/15 m48z08, m48z18
symbol parameter min max unit t pd e or w at v ih before power down 0 m s t f (1) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (2) v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 0 m s t rb v so to v pfd (min) v cc rise time 1 m s t rec e or w at v ih after power up 1 ms notes :1.v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 m s after v cc passes v pfd (min). 2. v pfd (min) to v so fall time of less than t fb may cause corruption of ram data. table 7. power down/up mode ac characteristics (t a = 0 to 70 c) ai00606 v cc inputs (per control input) outputs don't care high-z tf tfb tr trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so figure 5. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e high as v cc rises past v pfd (min). some systems may performs inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begins. even though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running. 5/15 m48z08, m48z18
symbol parameter m48z08 / 18 unit -100 min max t avav read cycle time 100 ns t avqv (1) address valid to output valid 100 ns t elqv (1) chip enable low to output valid 100 ns t glqv (1) output enable low to output valid 50 ns t elqx (2) chip enable low to output transition 10 ns t glqx (2) output enable low to output transition 5 ns t ehqz (2) chip enable high to output hi-z 50 ns t ghqz (2) output enable high to output hi-z 40 ns t axqx (1) address transition to output transition 5 ns notes: 1. c l = 100pf (see figure 4). 2. c l = 30pf (see figure 4). table 8. read mode ac characteristics (t a =0to70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) ai01385 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a12 e g dq0-dq7 valid figure 6. read mode ac waveforms 6/15 m48z08, m48z18
symbol parameter m48z08 / 18 unit -100 min max t avav write cycle time 100 ns t avwl address valid to write enable low 0 ns t avel address valid to chip enable low 0 ns t wlwh write enable pulse width 80 ns t eleh chip enable low to chip enable high 80 ns t whax write enable high to address transition 10 ns t ehax chip enable high to address transition 10 ns t dvwh input valid to write enable high 50 ns t dveh input valid to chip enable high 30 ns t whdx write enable high to input transition 5 ns t e1hdx chip enable high to input transition 5 ns t wlqz (1, 2) write enable low to output hi-z 50 ns t avwh address valid to write enable high 80 ns t aveh address valid to chip enable high 80 ns t whqx (1, 2) write enable high to output transition 10 ns notes: 1. c l = 30pf (see figure 4). 2. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. table 9. write mode ac characteristics (t a = 0 to 70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) read mode the m48z08,18 is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple- through ac- cess of data from eight of 65,536 locations in the static storage array. thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be available at the data i/o pins within t avqv (address access time) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g. if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the addressinputs are changed while e and g remain active, output data will remain valid for t axqx (output data hold time) but will go indeterminate until the next ad- dress access. write mode the m48z08,18 is in the write mode whenever w and e are active. the start of a write is referenced from the latter occurring falling edge of w or e. a write is terminated by the earlier rising edge of w or e. the addresses must be held valid throughout the cycle. e or w must return high of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g, a low on w will disable the outputs t wlqz after w falls. 7/15 m48z08, m48z18
ai01386 tavav twhax tdvwh data input a0-a12 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx figure 7. write enable controlled, write ac waveforms ai01387b tavav tehax tdveh a0-a12 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input figure 8. chip enable controlled, write ac waveforms 8/15 m48z08, m48z18
data retention mode with valid v cc applied, the m48z08,18 operates as a conventional bytewide ? static ram. should the supply voltage decay, the ram will automat- ically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as odon't care.o note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be as- sured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48z08,18 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recom- mended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data and powers the clock. the internal button cell will maintain data in the m48z08,18 for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min). e should be kept high as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to processor stabilization. normal ram operation can resume t rec after v cc exceeds v pfd (max). system battery life the useful life of the battery in the m48z08,18 is expected to ultimately come to an end for one of two reasons: either because it has been discharged while providing current to the ram in the battery back-up mode, or because the effects of aging render the cell useless before it can actually be completely discharged. the two effects are virtually unrelated allowing discharge, or capacity con- sumption, and the effects of aging, or storage life, to be treated as two independentbut simultaneous mechanisms. the earlier occurring failure mecha- nism defines the battery system life of the m48z08,18. ai01399 20 30 40 50 60 70 80 90 1 2 3 4 5 8 6 temperature (degrees celsius) 10 20 30 40 50 years t50% (average) t1% figure 9. predicted battery storage life versus temperature 9/15 m48z08, m48z18
cell storage life storage life is primarily a function of temperature. figure 9 illustrates the approximate storage life of the m48z08,18 battery over temperature. the re- sults in figure 9 are derived from temperature accelerated life test studies performed at sgs- thomson. for the purpose of the testing, a cell failure is defined as the inability of a cell stabilized at 25 c to produce a 2.4v closed circuit voltage across a 250 k w load resistor. the two lines, t 1% and t 50% , represent different failure rate distribu- tions for the cell's storage life. at 70 c, for example, the t 1% line indicates that an m48z08,18 has a 1% chance of having a battery failure 28 years into its life while the t 50% shows the part has a 50% chance of failure at the 50 year mark. the t 1% line repre- sents the practical onset of wear out and can be considered the worst case storage life for the cell. the t 50% can be considered the normal or average life. calculating storage life the following formula can be used to predict stor- age life: 1 {[(ta1/tt)/sl1]+[(ta2/tt)/sl2]+...+[(tan/tt)/sln]} where, ta1, ta2, tan = time at ambient temperature 1, 2, etc. tt = total time = ta1+ta2+...+tan sl1, sl2, sln = storage life at temperature 1, 2, etc. for example an m48z08,18 is exposed to tempera- tures of 55 c or less for 8322 hrs/yr, and tempera- tures greater than 60 c but less than 70 c for the remaining 438 hrs/yr. reading predicted t 1% values from figure 9, sl1 @ 200 yrs, sl2 = 28 yrs tt = 8760 hrs/yr ta1 = 8322 hrs/yr, ta2 = 438 hrs/yr predicted storage life 1 {[(8322/8760)/200]+[(431/8760)/28]} or 154 years. as can been seen from these calculations and the results, the expected lifetime of the m48z08, 18 should exced most system requirements. estimated system life since either storage life or capacity consumption can end the battery's life, the system life is marked by which ever occurs first. reference for system life each m48z08,18 is marked with a nine digit manu- facturing date code in the form of h99xxyyzz. for example, h995b9431 is: h = fabricated in carrollton, tx 9 = assembled in muar, malaysia, 9 = tested in muar, malaysia, 5b = lot designator, 9431 = assembled in the year 1994, work week 31. 10/15 m48z08, m48z18
ordering information scheme supply voltage and write protect voltage 08* v cc = 4.75v to 5.5v v pfd = 4.5v to 4.75v 18 v cc = 4.5v to 5.5v v pfd = 4.2v to 4.5v speed -100 100ns package pc pcdip28 mh soh28 temp. range 1 0to70 c 6** 40 to 85 c shipping method for so blank tubes tr tape &reel example: m48z18 -100 mh 1 tr the so and battery packages are shipped separately in plastic anti-static tubes. the so package is also available to ship in tape & reel form. for the m48t18 28 lead so, the battery package (i.e. snaphat) part number is om4z28-br00sh1o. for a list of available options (supply voltage, speed, package, etc...) refer to the current memory shortform catalogue. for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. notes: 08* caphat package only. 6** temperature range available for m48z18 product only. 11/15 m48z08, m48z18
pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28 pcdip28 drawing is not to scale pcdip28 - 28 pin plastic dip, battery caphat 12/15 m48z08, m48z18
soh e n d c l a1 a 1 h a cp be a2 eb symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 0.050 eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 soh28 drawing not to scale soh28 - 28 lead plastic small outline, battery snaphat 13/15 m48z08, m48z18
sh a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 sh28 sh28 - snaphat housing for 28 lead plastic small outline drawing not to scale 14/15 m48z08, m48z18
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved ? zeropower is a registered trademark of sgs-thomson microelectronics ? snaphat, caphat and bytewide are trademarks of sgs-thomson microelectronics sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 15/15 m48z08, m48z18
ai01027 11 a0-a10 w dq0-dq7 v cc m48t02 m48t12 g v ss 8 e figure 1. logic diagram m48t02 m48t12 cmos 2k x 8 timekeeper sram integrated ultra low power sram, real time clock and power-fail control circuit bytewide ram-like clock access bcd coded year, month, day, date, hours, minutes and seconds clock accuracy of 1 minute a month, @ 25 c software controlled clock calibration for high accuracy applications automatic power-fail chip deselect and write protection choice of two write protect voltages: m48t02: 4.5v v pfd 4.75v m48t12: 4.2v v pfd 4.5v self contained battery and crystal in the caphat dip package 10 years of data retention and clock operation in the absence of power pin and function compatible with jedec standard 2k x 8 srams description the m48t02,12 timekeeper ? ram is a 2k x 8 non-volatile static ram and real time clock which is pin and functional compatible with the mk48t02,12. a0-a10 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground table 1. signal names 24 1 pcdip24 (pc) battery caphat december 1994 1/14
symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) 40 to 85 c v io input or output voltages 0.3 to 7 v v cc supply voltage 0.3 to 7 v i o output current 20 ma p d power dissipation 1 w note: stresses greater than those listed under oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. caution: negative undershoots below 0.3 volts are not allowed on any pin while in the battery back-up mode. table 2. absolute maximum ratings mode v cc e g w dq0-dq7 power deselect 4.75v to 5.5v or 4.5v to 5.5v v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) x x x high z cmos standby deselect v so x x x high z battery back-up mode note :x=v ih or v il table 3. operating modes a1 a0 dq0 a7 a4 a3 a2 a6 a5 a10 a8 a9 dq7 w g e dq5 dq1 dq2 dq3 v ss dq4 dq6 v cc ai01028 m48t02 m48t12 8 1 2 3 4 5 6 7 9 10 11 12 16 15 24 23 22 21 20 19 18 17 14 13 figure 2. dip pin connections a special 24 pin 600mil dip caphat ? package houses the m48t02,12 silicon with a quartz crystal and a long life lithium button cell to form a highly integrated battery backed-up memory and real time clock solution. the m48t02,12 button cell has sufficient capacity and storage life to maintain data and clock function- ality for an accumulated time period of at least 10 years in the absence of power over the operating temperature range. the m48t02,12 is a non-volatile pin and function equivalent to any jedec standard 2k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. as figure 3 shows, the static memory array and the quartz controlled clock oscillator of the m48t02,12 are integrated on one silicon chip. the two circuits are interconnected at the upper eight memory lo- cations to provide user accessible bytewide ? description (cont'd) 2/14 m48t02, m48t12
ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k w device under test 1k w figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0.6v to 2.4v input and output timing ref. voltages 0.8v to 2.2v ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. ai01329 lithium cell oscillator and clock chain v pfd v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 biport sram array 2040 x 8 sram array a0-a10 dq0-dq7 e w g power bok figure 3. block diagram clock information in the bytes with addresses 7f8h- 7ffh. the clock locations contain the year, month, date, day, hour, minute, and second in 24 hour bcd format. corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. byte 7f8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport ? read/write memory cells. the m48t02,12 includes a clock control circuit which updates the clock bytes with current informa- tion once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t02,12 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system opera- tion brought on by low v cc .asv cc falls below approximately 3v, the control circuitry connects the battery which maintains data and clock operation until valid power returns. 3/14 m48t02, m48t12
symbol parameter test condition min max unit i li (1) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 5 m a i cc supply current outputs open 80 ma i cc1 (2) supply current (standby) ttl e = v ih 3ma i cc2 (2) supply current (standby) cmos e = v cc 0.2v 3 ma v il (3) input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = 1ma 2.4 v notes: 1. outputs deselected. 2. measured with control bits set as follows: r = '1'; w, st, ks, ft = '0'. 3. negative spikes of 1v allowed for up to 10ns once per cycle. table 5. dc characteristics (t a =0 to70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) symbol parameter test condition min max unit c in input capacitance v in =0v 10 pf c io (2) input / output capacitance v out =0v 10 pf notes: 1. effective capacitance calculated from the equation c = i d t/ d v with d v = 3v and power supply at 5v. 2. outputs deselected table 4. capacitance (1) (t a =25 c, f = 1 mhz ) symbol parameter min typ max unit v pfd power-fail deselect voltage (m48t02) 4.5 4.6 4.75 v v pfd power-fail deselect voltage (m48t12) 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr (2) expected data retention time 10 years notes: 1. all voltages referenced to v ss . 2. @ 25 c table 6. power down/up trip points dc characteristics (1) (t a =0to70 c) 4/14 m48t02, m48t12
symbol parameter min max unit t pd e or w at v ih before power down 0 m s t f (1) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (2) v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 0 m s t rb v so to v pfd (min) v cc rise time 1 m s t rec e or w at v ih after power up 2 ms notes :1.v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 50 m s after v cc passes v pfd (min). 2. v pfd (min) to v so fall time of less than t fb may cause corruption of ram data. table 7. power down/up mode ac characteristics (t a = 0 to 70 c) ai00606 v cc inputs (per control input) outputs don't care high-z tf tfb tr trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so figure 5. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e high as v cc rises past v pfd (min). some systems may performs inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begins. even though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running. 5/14 m48t02, m48t12
symbol parameter m48t02 / 12 unit -120 -150 -200 min max min max min max t avav read cycle time 120 150 200 ns t avqv address valid to output valid 120 150 200 ns t elqv chip enable low to output valid 120 150 200 ns t glqv output enable low to output valid 75 75 80 ns t elqx chip enable low to output transition 10 10 10 ns t glqx output enable low to output transition 5 5 5 ns t ehqz chip enable high to output hi-z 30 35 40 ns t ghqz output enable high to output hi-z 30 35 40 ns t axqx address transition to output transition 5 5 5 ns table 8. read mode ac characteristics (t a =0to70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) ai01330 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a10 e g dq0-dq7 valid figure 6. read mode ac waveforms 6/14 m48t02, m48t12
symbol parameter m48t02 / 12 unit -120 -150 -200 min max min max min max t avav write cycle time 120 150 200 ns t avwl address valid to write enable low 0 0 0 ns t avel address valid to chip enable low 0 0 0 ns t wlwh write enable pulse width 75 90 120 ns t eleh chip enable low to chip enable high 75 90 120 ns t whax write enable high to address transition 10 10 10 ns t ehax chip enable high to address transition 10 10 10 ns t dvwh input valid to write enable high 35 40 60 ns t dveh input valid to chip enable high 35 40 60 ns t whdx write enable high to input transition 5 5 5 ns t ehdx chip enable high to input transition 5 5 5 ns t wlqz write enable low to output hi-z 40 50 60 ns t avwh address valid to write enable high 90 120 140 ns t aveh address valid to chip enable high 90 120 140 ns t whqx write enable high to output transition 10 10 10 ns table 9. write mode ac characteristics (t a = 0 to 70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) read mode the m48t02,12 is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through ac- cess of data from eight of 16,384 locations in the static storage array. thus, the unique address specified by the 11 address inputs defines which one of the 2,048 bytes of data is to be accessed. valid data will be available at the data i/o pins within t avqv (address access time) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g. if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the addressinputs are changed while e and g remain active, output data will remain valid for t axqx (output data hold time) but will go indeterminate until the next ad- dress access. write mode the m48t02,12 is in the write mode whenever w and e are active. the start of a write is referenced from the latter occurring falling edge of w or e. a write is terminated by the earlier rising edge of w or e. the addresses must be held valid throughout the cycle. e or w must return high for minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus conten- tion; although, if the output bus has been activated by a low on e and g, a low on w will disable the outputs t wlqz after w falls. 7/14 m48t02, m48t12
ai01331 tavav twhax tdvwh data input a0-a10 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx figure 7. write enable controlled, write ac waveforms ai01332b tavav tehax tdveh a0-a10 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input figure 8. chip enable controlled, write ac waveforms 8/14 m48t02, m48t12
data retention mode with valid v cc applied, the m48t02,12 operates as a conventionalbytewide static ram. should the supply voltage decay, the ram will automatically power-fail deselect,write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as odon't care.o note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be as- sured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t02,12 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recom- mended. the power switching circuit connects external v cc to the ram and disconnects the battery when v cc rises above v so .asv cc rises, the battery voltage is checked. if the voltage is too low, an internal battery not ok (bok) flag will be set. the bok flag can be checked after power up. if the bok flag is set, the first write attempted will be blocked. the flag is automatically cleared after the first write, and normal ram operation resumes. figure 9 illus- trates how a bok check routine could be struc- tured. clock operations reading the clock updates to the timekeeper registers should be halted before clock data is read to prevent reading data in transition. because the biport time- keeper cells in the ram array are only data registers, and not the actual clock counters, updat- ing the registers can be halted without disturbing the clock itself. updating is halted when a '1' is written to the read bit, the seventh bit in the control register. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0'. setting the clock the eighth bit of the control register is the write bit. setting the write bit to a '1', like the read bit, halts updates to the timekeeper registers. the user can then load them with the correct day, date, and time data in 24 hour bcd format (see table 10). resetting the write bit to a '0' then transfers the values of all time registers (7f9h-7ffh) to the actual timekeeper counters and allows normal operation to resume. the ft bit and the bits marked as '0' in table 10 must be written to '0' to allow for normal timekeeper and ram operation. read data at any address ai00607 is data complement offirst read? (battery ok) power-up yes no write data complement back to same address read data at same address again notify system of low battery (data may be corrupted) write original data back to same address (battery low) continue figure 9. checking the bok flag status 9/14 m48t02, m48t12
stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. setting it to a '1' stops the oscillator. the m48t02,12is shipped from sgs-thomson with the stop bit set to a '1'. when reset to a '0', the m48t02,12 oscillator starts within 1 second. calibrating the clock the m48t02,12 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. a typical m48t02,12 is accurate within 1 minute per month at 25 c without calibration. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 c, which equates to about 1.53 minutes per month. of course the oscillation rate of any crystal changes with tem- perature. most clock chips compensate for crystal frequency and temperature shift error with cumber- some trim capacitors. the m48t02,12 design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in figure 10. the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits in the control register. this byte can be set to represent any value between 0 and 31 in binary form. the sixth bit is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. cali- bration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or - 5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. address data function/ran ge bcd format d7 d6 d5 d4 d3 d2 d1 d0 7ffh 10 years year year 00-99 7feh 0 0 0 10 m. month month 01-12 7fdh 0 0 10 date date date 01-31 7fch 0 ft 0 0 0 day day 01-07 7fbh ks 0 10 hours hours hour 00-23 7fah 0 10 minutes minutes minutes 00-59 7f9h st 10 seconds seconds seconds 00-59 7f8h w r s calibration control keys: s = sign bit ft = frequency test bit (set to '0' for normal clock operation) ks = kick start bit r = read bit w = write bit st = stop bit 0 = must be set to '0' table 10. register map 10/14 m48t02, m48t12
two methods are available for ascertaining how much calibration a given m48t02,12 may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final prod- uct is packaged in a non-user serviceable enclo- sure. all the designer has to do is provide a simple utility that accesses the calibration byte. the utility could even be menu driven and made foolproof. the second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the day register, is set to a '1', and the oscillator is running at 32,768 hz, the lsb (dq0) of the seconds reg- ister will toggle at 512 hz. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for exam- ple, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a -10(001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. the device must be selected and addresses must stable at address 7f9h when read- ing the 512 hz on dq0. the ft bit must be set using the same method used to set the clock, using the write bit. the lsb of the seconds register is monitored by holding the m48t02,12 in an extended read of the seconds register, without having the read bit set. the ft bit must be reset to '0' for normal clock operations to resume. ai00594 normal positive calibration negative calibration figure 10. clock calibration 11/14 m48t02, m48t12
ordering information scheme supply voltage and write protect voltage 02 v cc = 4.75v to 5.5v v pfd = 4.5v to 4.75v 12 v cc = 4.5v to 5.5v v pfd = 4.2v to 4.5v speed -120 120ns -150 150ns -200 200ns package pc pcdip24 temp. range 1 0to70 c example: m48t02 -120 pc 1 for a list of available options (supply voltage, speed, package, etc...) refer to the current memory shortform catalogue. for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. 12/14 m48t02, m48t12
pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.36 8.89 0.329 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 34.29 34.80 1.350 1.370 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 25.15 30.73 0.990 1.210 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n24 24 pcdip24 drawing is not to scale pcdip24 - 24 pin plastic dip, battery caphat 13/14 m48t02, m48t12
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved ? timekeeper, caphat, bytewide and biport are trademarks of sgs-thomson microelectronics sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 14/14 m48t02, m48t12
ai01186 11 a0-a10 w dq0-dq7 v cc m48z02 m48z12 g v ss 8 e figure 1. logic diagram m48z02 m48z12 cmos 2k x 8 zeropower sram integrated ultra low power sram, power-fail control circuit and battery unlimited write cycles read cycle time equals write cycle time automatic power-fail chip deselect and write protection choice of two write protect voltages: m48z02: 4.5v v pfd 4.75v m48z12: 4.2v v pfd 4.5v self contained battery in the caphat dip package 10 years of data retention in the absence of power pin and function compatible with jedec standard 2k x 8 srams description the m48z02,12 zeropower ? ram is a 2k x 8 non-volatile static ram which is pin and functional compatible with the mk48z02,12. a special 24 pin 600mil dip caphat ? package houses the m48z02,12 silicon with a long life lith- ium button cell to form a highly integrated battery backed-up memory solution. a0-a10 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground table 1. signal names 24 1 pcdip24 (pc) battery caphat december 1994 1/12
symbol parameter value unit t a ambient operating temperature grade 1 grade 6 0to70 40 to 85 c t stg storage temperature (v cc off) 40 to 85 c v io input or output voltages 0.3 to 7 v v cc supply voltage 0.3 to 7 v i o output current 20 ma p d power dissipation 1 w note: stresses greater than those listed under oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. caution: negative undershoots below 0.3 volts are not allowed on any pin while in the battery back-up mode. table 2. absolute maximum ratings mode v cc e g w dq0-dq7 power deselect 4.75v to 5.5v or 4.5v to 5.5v v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) x x x high z cmos standby deselect v so x x x high z battery back-up mode note :x=v ih or v il table 3. operating modes a1 a0 dq0 a7 a4 a3 a2 a6 a5 a10 a8 a9 dq7 w g e dq5 dq1 dq2 dq3 v ss dq4 dq6 v cc ai01187 m48z02 m48z12 8 1 2 3 4 5 6 7 9 10 11 12 16 15 24 23 22 21 20 19 18 17 14 13 figure 2. dip pin connections the m48z02,12 button cell has sufficient capacity and storage life to maintain data and clock function- ality for an accumulated time period of at least 10 years in the absence of power over the operating temperature range. the m48z02,12 is a non-volatile pin and function equivalent to any jedec standard 2k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the m48z02,12 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictablesystem opera- tion brought on by low v cc .asv cc falls below approximately 3v, the control circuitry connects the battery which maintains data and clock operation until valid power returns. description (cont'd) 2/12 m48z02, m48z12
ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k w device under test 1k w figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0.6v to 2.4v input and output timing ref. voltages 0.8v to 2.2v ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. ai01255 lithium cell v pfd v cc v ss voltage sense and switching circuitry 2k x 8 sram array a0-a10 dq0-dq7 e w g power figure 3. block diagram read mode the m48z02,12 is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through ac- cess of data from eight of 16,384 locations in the static storage array. thus, the unique address specified by the 11 address inputs defines which one of the 2,048 bytes of data is to be accessed. valid data will be available at the data i/o pins within t avqv (address access time) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g. if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the addressinputs are changed while e and g remain active, output data will remain valid for t axqx (output data hold time) but will go indeterminate until the next ad- dress access. 3/12 m48z02, m48z12
symbol parameter test condition min max unit i li (1) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 5 m a i cc supply current outputs open 80 ma i cc1 supply current (standby) ttl e = v ih 3ma i cc2 supply current (standby) cmos e = v cc 0.2v 3 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = 1ma 2.4 v note: 1. outputs deselected. table 5. dc characteristics (t a =0 to70 c or 40 to 85 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) symbol parameter test condition min max unit c in input capacitance v in =0v 10 pf c io (2) input / output capacitance v out =0v 10 pf notes: 1. effective capacitance calculated from the equation c = i d t/ d v with d v = 3v and power supply at 5v. 2. outputs deselected table 4. capacitance (1) (t a =25 c) symbol parameter min typ max unit v pfd power-fail deselect voltage (m48z02) 4.5 4.6 4.75 v v pfd power-fail deselect voltage (m48z12) 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr expected data retention time 10 years note: 1. all voltages referenced to v ss . table 6. power down/up trip points dc characteristics (1) (t a =0to70 c or 40 to 85 c) 4/12 m48z02, m48z12
symbol parameter min max unit t pd e or w at v ih before power down 0 m s t f (1) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (2) v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 0 m s t rb v so to v pfd (min) v cc rise time 1 m s t rec e or w at v ih after power up 2 ms notes :1.v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 50 m s after v cc passes v pfd (min). 2. v pfd (min) to v so fall time of less than t fb may cause corruption of ram data. table 7. power down/up mode ac characteristics (t a = 0 to 70 c or 40 to 85 c) ai00606 v cc inputs (per control input) outputs don't care high-z tf tfb tr trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so figure 5. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e high as v cc rises past v pfd (min). some systems may performs inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begins. even though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running. 5/12 m48z02, m48z12
symbol parameter m48z02 / 12 unit -120 -150 -200 min max min max min max t avav read cycle time 120 150 200 ns t avqv address valid to output valid 120 150 200 ns t elqv chip enable low to output valid 120 150 200 ns t glqv output enable low to output valid 75 75 80 ns t elqx chip enable low to output transition 10 10 10 ns t glqx output enable low to output transition 5 5 5 ns t ehqz chip enable high to output hi-z 30 35 40 ns t ghqz output enable high to output hi-z 30 35 40 ns t axqx address transition to output transition 5 5 5 ns table 8. read mode ac characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) ai01330 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a10 e g dq0-dq7 valid figure 6. read mode ac waveforms 6/12 m48z02, m48z12
symbol parameter m48z02 / 12 unit -120 -150 -200 min max min max min max t avav write cycle time 120 150 200 ns t avwl address valid to write enable low 0 0 0 ns t avel address valid to chip enable low 0 0 0 ns t wlwh write enable pulse width 75 90 120 ns t eleh chip enable low to chip enable high 75 90 120 ns t whax write enable high to address transition 10 10 10 ns t ehax chip enable high to address transition 10 10 10 ns t dvwh input valid to write enable high 35 40 60 ns t dveh input valid to chip enable high 35 40 60 ns t whdx write enable high to input transition 5 5 5 ns t ehdx chip enable high to input transition 5 5 5 ns t wlqz write enable low to output hi-z 40 50 60 ns t avwh address valid to write enable high 90 120 140 ns t aveh address valid to chip enable high 90 120 140 ns t whqx write enable high to output transition 10 10 10 ns table 9. write mode ac characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) write mode the m48z02,12 is in the write mode whenever w and e are active. the start of a write is referenced from the latter occurring falling edge of w or e. a write is terminated by the earlier rising edge of w or e. the addresses must be held valid throughout the cycle. e or w must return high for minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus conten- tion; although, if the output bus has been activated by a low on e and g, a low on w will disable the outputs t wlqz after w falls. 7/12 m48z02, m48z12
ai01331 tavav twhax tdvwh data input a0-a10 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx figure 7. write enable controlled, write ac waveforms ai01332b tavav tehax tdveh a0-a10 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input figure 8. chip enable controlled, write ac waveforms 8/12 m48z02, m48z12
data retention mode with valid v cc applied, the m48z02,12 operates as a conventional bytewide ? static ram. should the supply voltage decay, the ram will automat- ically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as odon't care.o note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be as- sured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48z02,12 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recom- mended. the power switching circuit connects external v cc to the ram and disconnects the battery when v cc rises above v so .asv cc rises, the battery voltage is checked. if the voltage is too low, an internal battery not ok (bok) flag will be set. the bok flag can be checked after power up. if the bok flag is set, the first write attempted will be blocked. the flag is automatically cleared after the first write, and normal ram operation resumes. figure 9 illus- trates how a bok check routine could be struc- tured. read data at any address ai00607 is data complement offirst read? (battery ok) power-up yes no write data complement back to same address read data at same address again notify system of low battery (data may be corrupted) write original data back to same address (battery low) continue figure 9. checking the bok flag status 9/12 m48z02, m48z12
ordering information scheme supply voltage and write protect voltage 02 v cc = 4.75v to 5.5v v pfd = 4.5v to 4.75v 12 v cc = 4.5v to 5.5v v pfd = 4.2v to 4.5v speed -120 120ns -150 150ns -200 200ns package pc pcdip24 temp. range 1 0to70 c 6 40 to 85 c example: m48z02 -120 pc 1 for a list of available options (supply voltage, speed, package, etc...) refer to the current memory shortform catalogue. for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. 10/12 m48z02, m48z12
pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.36 8.89 0.329 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 34.29 34.80 1.350 1.370 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 25.15 30.73 0.990 1.210 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n24 24 pcdip24 drawing is not to scale pcdip24 - 24 pin plastic dip, battery caphat 11/12 m48z02, m48z12
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved ? zeropowe r is a registered trademark of sgs-thomson microelectronics ? caphat and bytewide are trademarks of sgs-thomson microelectronics sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 12/12 m48z02, m48z12
ai01061 osci v cc mk41t56 v ss scl osco sda ft/out v bat figure 1. logic diagram mk41t56 cmos 64 x 8 serial access timekeeper sram counters for seconds, minutes, hours, day, date, month and years software clock calibration automatic power fail detect and switch circuitry i 2 c bus compatible 56 bytes of general purpose ram ultra-low battery supply current of 500na available with an operating temperature of 40 to 85 c automatic leap year compensation description the mk41t56 timekeeper ? ram is a low power 512 bit static cmos ram organized as 64 words by 8 bits. a built-in 32.768 khz oscillator (external crystal controlled) and the first 8 bytes of the ram are used for the clock/calendar function and are configured in bcd format. addresses and data are transferred serially via a two-line bi-direc- tional bus. the built-in address register is incre- mented automatically after each write or read data byte. the mk41t56 clock has a built-in power sense circuit which detects power failures and automaticallyswitches to the battery supply during power failures. the energy needed to sustain the ram and clock operations can be supplied from a small lithium button cell. osci oscillator input ocso oscillator output ft/out frequency test / output driver sda serial data address input / output scl serial clock v bat battery supply voltage v cc supply voltage v ss ground table 1. signal names 8 1 psdip8 (n) 0.4mm frame 8 1 so8 (s) 0.15mm frame november 1994 1/14
symbol parameter value unit t a ambient operating temperature 0 to 70 40 to 85 c t stg storage temperature (v cc off, oscillator off) 55 to 125 c v io input or output voltages 0.3 to 7 v v cc supply voltage 0.3 to 7 v i o output current 20 ma p d power dissipation 0.25 w note: stresses greater than those listed under oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. caution: negative undershoots below 0.3 volts are not allowed on any pin while in the battery back-up mode. table 2. absolute maximum ratings sda v ss scl ft/out osco osci v cc v bat ai00585c mk41t56 1 2 3 4 8 7 6 5 figure 2a. dip pin connections 1 sda v ss scl ft/out osco osci v cc v bat ai01062b mk41t56 2 3 4 8 7 6 5 figure 2b. so pin connections address data function/ran ge bcd format d7 d6 d5 d4 d3 d2 d1 d0 0 st 10 seconds seconds seconds 00-59 1 x 10 minutes minutes minutes 00-59 2 x x 10 hours hours hour 00-23 3 x x x x x day day 01-07 4 x x 10 date date date 01-31 5 x x x 10 m. month month 01-12 6 10 years years year 00-99 7 out ft s calibration control keys: s = sign bit; ft = frequency test bit; st = stop bit; out = output level; x = don't care. table 3. register map 2/14 mk41t56
typical data retention time is in excess of 10 years with a 39 ma/h 3v lithium cell. the mk41t56 clock is supplied in 8 pin plastic dual-in-line and 8 pin plastic small outline packages. operation the mk41t56 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct address (d0). the 64 bytes contained in the device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. hours register 4. day register 5. date register 6. month register 7. years register 8. control register 9 to 64. ram description (cont'd) ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k w device under test 1k w figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. ai00586b seconds oscillator 32.768 khz power on reset serial bus interface divider control logic address register minutes hours day date month year control ram (56 x 8) osci osco ft/out v cc v ss v bat scl sda 1hz figure 3. block diagram 3/14 mk41t56
symbol parameter test condition min typ max unit i li input leakage current 0v v in v cc 10 m a i lo output leakage current 0v v out v cc 10 m a i cc1 supply current scl/sda = v cc 0.3v 1 ma i cc2 supply current (standby) 1 ma v il input low voltage 0.3 1.5 v v ih input high voltage 3 v cc + 0.8 v v ol output low voltage i ol = 5ma, v cc = 4.5v 0.4 v v bat (1) battery supply voltage 2.6 3 3.5 v i bat battery supply current t a =25 c, v cc =0v, oscillator on, v bat =3v 450 500 na note: sgs-thomson recommends the rayovac br1225 or equivalent as the battery supply. table 5. dc characteristics (t a =0 to70 c or 40 to 85 c; v cc = 4.5v to 5.5v) symbol parameter min max unit c in input capacitance (scl) 7 pf c out (2) output capacitance (sda, ft/out) 10 pf notes: 1. effective capacitance calculated from the equation c = i d t/ d v with d v = 3v and power supply at 5v. 2. outputs deselected. table 4. capacitance (1) (t a =25 c, f = 1 mhz ) symbol parameter min typ max unit v pfd power-fail deselect voltage 1.2 v bat 1.25 v bat 1.285 v bat v v so battery back-up switchover voltage v bat v note: 1. all voltages referenced to v ss . table 6. power down/up trip points dc characteristics (1) (t a = 0 to 70 c or 40 to 85 c) symbol parameter min typ max unit f o resonant frequency 32.768 khz r s series resistance 35 k w c l load capacitance 12.5 pf notes: load capacitors are internally supplied with the mk41t56. circuit board layout considerations for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account. sgs-thomson recommends the ecs-.327-12.5-8sp-2 quartz crystal for industrial temperature operations. esc inc. can be contacted at 800-237-1041 or 913-782-7787 for further information on this crystal type. table 7. crystal electrical characteristics (externally supplied) 4/14 mk41t56
symbol parameter min max unit t pd scl and sda at v ih before power down 0 ns t fb v pfd (min) to v so v cc fall time 300 m s t rb v so to v pfd (min) v cc rise time 100 m s t rec scl and sda at v ih after power up 200 m s table 8. power down/up mode ac characteristics (t a = 0 to 70 c or 40 to 85 c) ai00595 v cc tfb trec tpd trb v pfd v so data retention time sda scl i bat figure 5. power down/up mode ac waveforms operation (cont'd) the mk41t56 clock continually monitors v cc for an out of tolerance condition. should v cc fall below v pfd the device terminates an access in progress and resets the device address counter.inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. when v cc falls below v bat the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. upon power up the device switches from battery to v cc at v bat and recognizes inputs when v cc goes above v pfd volts. 2-wire bus characteristics this bus is intended for communication between different ics. it consists of two lines: one bi-direc- tional for data signals (sda) and one for clock signals (scl). both the sda and the scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. 5/14 mk41t56
symbol parameter min max unit f scl scl clock frequency 0 100 khz t low clock low period 4.7 m s t high clock high period 4 m s t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 4 m s t su:sta start condition setup time (only relevant for a repeated start condition) 4.7 m s t su:dat (1) data setup time 250 ns t hd:dat data hold time 0 m s t su:sto stop condition setup time 4.7 m s t buf time the bus must be free before a new transmission can start 4.7 m s t i noise suppresion time constant at scl and sda input 0.25 1 m s note: 1. transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of scl. table 9. ac characteristics (t a =0to70 c or 40 to 85 c; v cc = 4.5v to 5.5v) accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is trans- mitted byte-wide and each receiver acknowledges with a nineth bit. within the bus specifications a low speed mode (2khz clock rate) and a high speed mode (100khz clock rate) are defined. the mk41t56 clock works in both modes. by definition a device that gives out a message is called otransmittero, the receiving device that gets the message is called oreceivero. the device that controls the message is called omastero. the devices that are controlled by the master are called oslaveso. acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge re- lated clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. also a master receiver must generatean acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal 2-wire bus characteristics (cont'd) 6/14 mk41t56
ai00587 data clock data line stable data valid start condition change of data allowed stop condition figure 6. serial bus data transfer sequence ai00588 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 data 1 data 2 data 8 figure 7. acknowledgement sequence ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p figure 8. bus timing requirements sequence 7/14 mk41t56
2-wire bus characteristics (cont'd) an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. write mode in this mode the master transmitter transmits to the mk41t56 slave receiver. bus protocol is shown in figure 10. following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addressed device that word address a n will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the mk41t56 slave re- ceiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte, see figure 9. read mode in this mode the master reads the mk41t56 slave after setting the slave address, see figure 11. fol- lowing the write mode control bit (r/w = 0) and the acknowledge bit, the word address a n is written to the on-chip address pointer. next the start con- dition and slave address are repeated followed by the read mode control bit (r/w = 1). at this point the master transmitter becomes the master re- ceiver. the data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the ad- dress pointer is only incremented on reception of an acknowledge bit. the mk41t56 slave transmit- ter will now place the data byte at address an + 1 on the bus, the master receiver reads and acknow- ledges the new byte and the address pointer is incremented to an + 2. this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter. an alternate read mode may also be imple- mented whereby the master reads the mk41t56 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer, see figure 12. clock calibration the mk41t56 is driven by a quartz controlled os- cillator with a nominal frequency of 32,768 hz. a typical mk41t56 is accurate within 1 minute per month at 25 c without calibration. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 c, which equates to about 1.53 minutes per month. of course the oscillation rate of any crystal changes with tem- perature. most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. the mk41t56 design, however, em- ploys periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in figure 13. the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits in the control register. this byte can be set to represent any value between 0 and 31 in binary form. the sixth bit is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. cali- bration occurs within a 64 minutes cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 min- utes cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is + 4.068 or 2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768 hz, ai00590 r/w slave address start a 01000 11 figure 9. slave address location 8/14 mk41t56
ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (n) slave address figure 10. write mode sequence ai00592b bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (n) slave address s start r/w slave address ack figure 11. read mode sequence ai00593 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address figure 12. alternate read mode sequence 9/14 mk41t56
clock calibration (cont'd) each of the 31 increments in the calibration byte would represent 10.7 seconds per month. two methods are available for ascertaining how much calibration a given mk41t56 may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final prod- uct is packaged in a non-user serviceable enclo- sure. all the designer has to do is provide a simple utility that accessed the calibration byte. the utility could even be menu driven and made foolproof. the second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the con- trol register, is set to a '1', and the oscillator is running at 32,768 hz, the ft/out pin of the device will toggle at 512 hz. any deviation from 512 hz indicates the degree and direction of oscillator fre- quency shift at the test temperature. for example, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, re- quiring a 10(001010) to be loaded into the cali- bration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. output driver pin when the ft bit is not set the ft/out pin becomes an output driver that reflects the contents of d7 of the control register. in other words when d6 of location 7 is a zero and d7 of location 7 is a zero and then the ft/out pin will be driven low. note: the ft/out pin is open drain which requires an external pull-up resistor. ai00594 normal positive calibration negative calibration figure 13. divide by 128 stage 10/14 mk41t56
ordering information scheme operating temp. blank 0 to 70 c i* 40 to 85 c package n psdip8 0.4mm frame s so8 0.15mm frame speed 00 no speed options shipping method for so blank tubes tr tape & reel example: mki41t56 n 00 tr for a list of available options refer to the current memory shortform catalogue. for furtherinformation or any aspect of this device, please contact the sgs-thomson sales office nearest to you. note: i* available in the so package only. 11/14 mk41t56
psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b symb mm inches typ min max typ min max a 4.80 0.189 a1 0.70 0.028 a2 3.10 3.60 0.122 0.142 b 0.38 0.58 0.015 0.023 b1 1.15 1.65 0.045 0.065 c 0.38 0.52 0.015 0.020 d 9.20 9.90 0.362 0.390 e 7.62 0.300 e1 6.30 7.10 0.248 0.280 e1 2.54 0.100 ea 8.40 0.331 eb 9.20 0.362 l 3.00 3.80 0.118 0.150 n8 8 psdip8 drawing is not to scale psdip8 - 8 pin plastic skinny dip, 0.4mm lead frame 12/14 mk41t56
so-a e n cp b e a d c l a1 a 1 h hx45 symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 so8 drawing is not to scale so8 - 8 lead plastic small outline, 150 mils body width 13/14 mk41t56
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved ? timekeeper is a trademark of sgs-thomson microelectronics purchase of i 2 c components by sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 14/14 mk41t56

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